By Dave Durfee, Chief Scientist
Manufacturer of High-Speed Serial Data Equipment
Developing a reliable external device to buffer high-speed serial data to ensure no data packets were dropped during transit to the PC-based test system.
The client’s existing PC-based test system was unable to keep up with the high-volume, high-speed serial data produced by their product, resulting in packet loss. Key requirements for the new solution included:
Interfacing seamlessly with existing equipment.
Buffering data to prevent packet loss.
Handling multiple high-speed data streams simultaneously without failure.
Recognizing Impact ES–Rhode Island’s expertise in hardware and software integration, the client turned to us for a robust solution that would maintain data integrity.
Impact ES–Rhode Island designed and developed a custom device leveraging the Xilinx Zynq chipset, a powerful combination of ARM processors and FPGA, to meet the client’s requirements effectively.
Chipset Selection: The Xilinx Zynq chipset was chosen for its integrated ARM processor and FPGA, which allowed simultaneous high-speed data handling and buffering.
Custom IP Development: Using the Vivado toolchain, Impact ES–Rhode Island developed a custom FPGA serial IP block to process the high-speed data. The Xilinx-provided IP block could not meet the required speed, so a custom solution ensured seamless operation.
Bare Metal Approach: After evaluating Linux, RTOS, and bare metal programming, Impact ES–Rhode Island opted for a bare metal approach for coding the ARM processor. This decision provided the optimal balance of performance and simplicity for the project.
The system was designed to buffer and transmit three simultaneous high-speed data streams without loss.
Rigorous testing ensured the system could operate continuously for 24 hours with zero packet loss, exceeding client expectations.
The final solution provided a reliable, high-performance external device that met all client requirements. Key results included:
Improved Data Integrity: The system successfully buffered and transmitted high- speed serial data streams without loss over extended periods.
Custom FPGA Block: The tailored FPGA IP block ensured the system could handle the client’s high-speed data requirements.
Optimized Performance: The bare metal approach delivered a streamlined, efficient solution tailored to the client’s specific needs.
Impact ES–Rhode Island’s expertise in Xilinx Zynq chipsets and Vivado toolchain enabled the development of a custom solution tailored to high-speed data buffering.
The decision to use a bare metal programming approach provided a simplified yet effective way to achieve optimal performance.
Collaboration and innovation ensured the delivery of a solution that surpassed the client’s expectations and safeguarded data integrity.
This case study exemplifies Impact ES–Rhode Island’s commitment to delivering innovative solutions for complex hardware and software challenges.
